Intel® Xeon® 5500 Processor is good news for HPC

April 7th, 2009 11:53 am
Posted by Steve Conway
Tags: , , , ,

The arrival of the new Intel® Xeon® 5500 processor will be welcome news for the High Performance Computing (HPC) community, from entry-level to high-end users. The Intel® Xeon® 5500 is designed to provide the per-core bandwidth that has been needed to advance performance on key scientific and engineering applications. And Xeon’s  bandwidth boost, in combination with the Intel Cluster Ready (ICR) program, should make it even easier for the growing contingent of new and less-experienced users to benefit from HPC.

The bytes/flops ratio of HPC systems has been out of whack for decades, causing the systems to become increasingly "flopsided." Clusters with multi-core processors dramatically worsened the ratio as core counts repeatedly doubled without corresponding increases in bandwidth. Primarily due to superior price/performance based on the use of x86 processors and other standard technologies, clusters have become the dominant species of HPC servers, capturing 65% of market revenue in 2007 and increasing their share in 2008. But clusters also pose some of the trickiest challenges ever encountered by HPC system administrators and end-users.

It's not just the per-core bandwidth issue. The ballooning of cluster sizes and component counts has made clusters more challenging to manage and efficiently exploit. As vendors have made progress in taming clusters, cluster complexity has raced out ahead of them. For this reason, cluster users report essentially the same pain points today as they reported five years ago.

Intel® faced off against cluster complexity in 2007 by launching the Intel® Cluster Ready program, a standard ("reference") architecture that pre-tests hardware and software components together to help ensure that they will inter-operate right out of the box. ICR isn't the only HPC standard cluster architecture, but it's the best known one and isn't restricted to a single OEM. ICR started in 2007 with three vendors and today qualifies components from 150 hardware and software vendor-members.

A program like Intel® Cluster Ready is particularly important for new and less-experienced HPC users. Most of these users fit into IDC's "workgroup" HPC segment for systems priced at under $100,000. Workgroup users are found both in smaller firms, such as engineering services suppliers, and in smaller units within tier 1 organizations. They typically lack access to HPC-proficient IT staff. ICR is designed to help meet their "ease-of-everything" requirements and prevent them from having to become their own system integrators. In late 2007 and throughout 2008, half a dozen OEMs introduced new HPC server products for the workgroup segment, and many of these OEMs are ICR members.

Intel® is the processor market share leader among existing HPC users. By making it easier to scale important classes of applications on multi-core processors, the new  Xeon® 5500 should give a leg up to new and relatively new technical computing users – the same contingent that increasingly relies on standard architectures like ICR to get them over the HPC complexity hurdle. Alone, the Xeon® 5500 promises to benefit a wide range of HPC users, including at the high end, by injecting better balance into the bytes/flops ratio. Together, Xeon® and ICR have the potential to become a powerful catalyst for accelerating HPC adoption and use, especially in the workgroup segment.


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Author Info

Steve Conway, Research Vice President in IDC's High Performance Computing group, plays a major role in directing and implementing HPC research related to the worldwide market for technical servers and supercomputers. A 20-year veteran of the HPC and IT industries, Mr. Conway co-authors key IDC studies, reports and white papers, helps organize and advance the HPC User Forum, and provides thought leadership and practical guidance for users, vendors and other members of the HPC community.

Before joining IDC, Mr. Conway was vice president of corporate communications and investor relations for Cray Inc. and headed corporate communications for Cray Research and CompuServe Corporation. He had a 12-year career in university teaching and administration at Boston University and Harvard University. A former Senior Fulbright Fellow, he holds bachelor's and master's degrees in German from Columbia University and a master's in comparative literature from Brandeis University, where he also completed doctoral coursework and exams.